The DFT Outline Generation Command
Description:
The DFT Outline Generation
menu command or toolbar button allows the user to create the
component outlines to be used for Design for Testability purposes.
CAMCAD needs to have closed polylines surrounding the
components, underneath which we can analyze for blocked features.
However, the ECAD data may or may not have usable component
outlines. This Outline Generation command works quickly to
create outlines on DFT_OUTLINE_TOP and DFT_OUTLINE_BOT layers.
Menu Location: Tools | DFT Analysis
| DFT Outline Generation
Hot Key: N/A
Toolbar Location: N/A
Toolbar Button: N/A
Details
Execute this command to create new DFT outlines for geometries.
Click the Select All button
to select all Geometries in the ECAD file. If just a subset
of geometries are desired, use shift-click or ctrl-click
in the Geometries window to select the desired symbols. With
the components selected, click the Process
button to create DFT Outlines for those geometries.
The DFT Outline Generation dialog has several options for
users to adjust:
- Body Outline Calculation: This option analyzes
the silkscreen present in the ECAD file, and makes a new
DFT outline based on the "Primary Component Outline".
It completes component body outlines when they are not closed
polylines.
- Pin Center Calculation: This option will generate
a DFT Outline, extending to the center of all pins in the
device. This is recommended for SOIC and QFP type devices.
- Body/Pad Extents Calculation: This option makes
a DFT Outline that lies outside the pin extents, but also
includes all of the visible elements of the geometry.
- Inside Pads Calculation: This option makes a DFT
Outline that lies inside the pin extents of the geometries
selected.
- Load DFT Outline from External Library: This option
makes a DFT Outline that comes from an external library
(i.e. RealPart) Not Yet Implemented.
The Rectangle Outlines option forces CAMCAD
to create rectangular outlines for all selected components.
The Overwrite Existing DFT Outline option will
create new DFT Outlines, removing old ones.
The Include Single Pin Components is an option
for allowing or unallowing single pin components from getting
a DFT outline.
- Note: Testpoints in ECAD data may have silkscreen
component outlines. If you choose the Include Single Pin
Components option and then create DFT outlines, the testpoints
may be assigned a DFT outline. Later, when Access Analysis
is performed, these DFT Outlines surrounding your testponts
may render the TPs not accessible. Therefore, if you have
testpoints in your ECAD file, and if they are type PCB
Component as opposed to VIAs, you should not use the Include
Single Pin Components option.
Pre-DFT Outline Generation
Post-DFT Outline Generation
See Also
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